AI New Prosperity》CoWoS production capacity is insufficient to meet the demand for AI chips, Taiwanese manufacturers are actively expanding production

2024/02/21

With the booming development of technologies such as AI, cloud, big data analysis, and mobile computing, modern society has increasingly higher demands for computing power. After 3 nanometers, wafer size has reached physical limits and manufacturing costs have increased. For reasons such as this, in addition to continuing to develop advanced manufacturing processes, the semiconductor industry is also looking for other ways to maintain a small size of chips while maintaining high performance. The concept of "heterogeneous integration" has thus emerged in contemporary science, and chips have also evolved from The original single layer turned to multi-layer stacked advanced packaging.

CoWoS, which is often seen in the media, can be broken down into the following definition to explain. Cow is "Chip-on-Wafer", which refers to chip stacking. WoS "Wafer-on-Substrate" stacks wafers on a substrate. Therefore, CoWos means stacking chips and packaging them on a substrate.

This can reduce the space required for the chip and also achieve the benefits of reducing power consumption and cost. Among them, it can be divided into 2.5D horizontal stacking (the most well-known is TSMC's CoWoS) and 3D vertical stacking version. Different processors, memories and other chip modules are stacked layer by layer to make small chips (Chiplet). Because its main application is in advanced processes, it is also called advanced packaging.

According to data from market research and survey agency TrendForce, you can get a feel for the popularity of the AI chip market. In 2023, AI servers (including equipped with GPU, FPGA, ASIC, etc.) will be shipped nearly 1.2 million units, an increase of 38.4% from 2022, accounting for nearly 9% of overall server shipments. If the time is extended to 2026, the proportion is expected to reach 15%, and the compound annual growth rate of AI server shipments from 2022 to 2026 will be 22%. Under this circumstance, AI chip shipments will grow by 46% in 2023.

Since AI chips require advanced packaging technology, TSMC’s 2.5D advanced packaging CoWoS technology is currently the main technology used in AI chips. The GPU uses a higher specification HBM, which requires 2.5D advanced packaging technology to integrate the core dies. The front-end chip stacking (Chip on Wafer) process of CoWoS packaging is mainly manufactured through 65 nanometers in the wafer factory, and then silicon through hole etching is performed. The completed product is then packaged on the carrier board by stacking chips ( Wafer on Substrate).

Therefore, the production capacity of CoWoS packaging technology has become a major bottleneck in AI chip output in the past year, and is also the key to whether the demand for AI chips can be met in 2024. Foreign investors have previously pointed out that Huida is currently the largest customer of TSMC’s 2.5D advanced packaging CoWoS technology. Both the Huida H100 GPU, which uses TSMC's 4nm advanced process, and the A100 GPU, which uses TSMC's 7nm process, are packaged using CoWoS technology. As a result, Huida's chips account for 40% to 50% of TSMC's CoWoS production capacity. . This is why the hot sales of Huida chips have led to tight supply of TSMC’s CoWoS packaging capacity.

TSMC's production expansion expected to ease tight situation in 2024

At a corporate briefing held in July 2023, TSMC stated that it expected to double its CoWoS production capacity and that the market supply shortage would be alleviated by the end of 2024. Subsequently, TSMC announced in late July 2023 that it would spend nearly NT$90 billion to establish an advanced packaging wafer fab in Tongluo Science Park. It is expected to complete the construction of the fab by the end of 2026, with mass production scheduled for the second quarter of 2027. Or between Season 3.

In addition, at the press conference on January 18, 2024, TSMC Chief Financial Officer Huang Renzhao also emphasized that TSMC will continue to expand production of advanced processes in 2024. Therefore, 10% of the full-year capital expenditures will be estimated expenditures for the expansion of production capacity such as advanced packaging, testing, and photomasks.

In fact, Huida Financial Colette Kress previously stated at an investor meeting that Huida has developed and certified the production capacity of other suppliers in the key process of CoWoS advanced packaging, and it is expected that supply will gradually increase in the next few quarters. In this regard, foreign investor JPMorgan Chase pointed out that the key reason for the bottleneck in CoWoS production capacity is that the supply of intermediaries exceeds demand. The reason is that the interposer silicon perforation process is complex, and capacity expansion requires more high-precision equipment. However, high-precision equipment has a long delivery time, and existing equipment also requires regular cleaning and inspection, resulting in short supply.

At present, in addition to TSMC's CoWoS dominating the advanced packaging market, UMC, ASE Investment Controls, Silicon Products, Licheng, etc. are also gradually entering the CoWoS advanced packaging market. Among them, when it comes to deploying 2.5D advanced packaging interposer production capacity, UMC also stated at a conference in late July 2023 that it will accelerate the development of the silicon interposer technology and production capacity required by customers.

UMC plans interposer production capacity, and ASE launches VIPack advanced packaging platform

UMC emphasizes that the company is the first wafer foundry in the world to provide open system solutions for silicon intermediary manufacturing. Through this open system (UMC+OSAT) cooperation model, it can provide a complete and verified supply chain to quickly introduce mass production. . In addition, UMC's 2.5D open system solution is based on the 2.5D TSI silicon interposer wafer produced by UMC, and the advanced chip packaging services of world-class packaging and testing plants, successfully cooperating to establish a certified and complete 2.5D TSI silicon interposer. Wafer packaging supply chain.

Currently accounting for approximately 32% of the global semiconductor back-end professional packaging and testing foundry (OSAT) industry shipments, and accounting for more than 50% of Taiwan's OSAT shipments, ASE Investment Holdings, the leader in packaging and testing, also stated that its subsidiary ASE Semiconductor has stated that the recent CoWoS The topic of packaging technology is hotly debated, and ASE Investment and Control itself is also developing advanced packaging and is a close partner with TSMC.

ASE emphasized that it previously launched the VIPack advanced packaging platform to provide vertical interconnection integrated packaging solutions. VIPack is ASE’s next-generation 3D heterogeneous integration architecture that extends design rules and enables ultra-high density and performance designs. This platform leverages advanced redistribution layer (RDL) processes, embedded integration, and 2.5D/3D packaging technologies to help customers integrate multiple dies in a single package to achieve unprecedented innovative applications.

In addition, ASE has also laid out a number of packaging technologies in the fields of high-performance computing (HPC) and AI, which can help AI applications imitate human five-sense applications, such as 2.5D and 3D IC, co-packaged optical components (CPO), double-sided die ( double side mold), antenna packaging (Antenna in Package), embedded die SESUB, etc. It is expected that ASE’s advanced packaging performance will double in 2024.

PowerCheng joins hands with Winbond to provide heterogeneous integrated packaging technology

In addition, Licheng Technology, a major packaging and testing company, is also actively deploying advanced packaging related to logic chips and AI applications. Previously, it was stated at the conference that PowerCheng is seeking to form alliances and cooperation with wafer fabs to develop interposers with fine line width and fine diameter through silicon through holes (TSV), and provide customers with relevant CoWoS advanced packaging options. It is expected to be the fastest CoWoS-related advanced packaging products will be available in the second half of 2024. At present, memory giant Winbond has stated that with the rapid evolution of AI technology, the market demand for high bandwidth and high-speed computing has surged, which in turn has driven the demand for advanced packaging and heterogeneous integration technology. Therefore, Winbond and Licheng Technology jointly lead this technology wave to provide heterogeneous integrated packaging technology.

Regarding the cooperation with LiCheng Technology, Winbond stated that the cooperation business will be carried out in the form of development project cooperation, including that Winbond will provide CUBE (customized ultra-high bandwidth components) DRAM, as well as customized silicon interposers, while integrating Decoupling Capacitor (Decoupling Capacitor) and other advanced technologies, combined with the 2.5D and 3D packaging services provided by Licheng Technology.

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