IMPACT 2023, Asia's largest packaging and circuit board event, focuses on the latest trends in advanced packaging, carrier boards and AI

2023/11/30

The "18th International Assembly and Circuit Board Symposium – IMPACT 2023" was held earlier from October 25th to 27th at Taipei Nangang Exhibition Hall 1, organized by IEEE EPS-Taipei Electronic Packaging Society Taipei Branch, IMAPS-Taiwan The event is jointly held by the Taiwan International Microelectronics and Construction Society, Industrial Research Institute and TPCA Taiwan Circuit Board Association.

At the opening meeting on the first day, Dr. Luo Weizhong, chairman of the IMPACT 2023 conference, chairman of IMAPS-Taiwan and deputy director of the Institute of Electro-Optical Systems of ITRI, said that there were more than 700 participants this year, and nearly 30% of them were from overseas, which made IMPACT 2023 the current The most attended advanced packaging event in Asia. In this regard, he is particularly grateful to the IEEE EPS Headquarters, IMAPS, International Electronics Manufacturers Alliance (iNEMI), Japan Friendship Association, including the International Symposium on Electronic Packaging Technology (ICEP), Japan Institute of Electronics Packaging (JIEP), etc., as well as the industry and academia strong support.

Innovative advancement of key 3D packaging technologies and system-level performance expansion will usher in a new wave of AI applications

After the opening ceremony, Jun He, deputy general manager of TSMC's Quality and Reliability Organization and Advanced Packaging Technology and Services, and Raja Swaminathan, corporate vice president of AMD, delivered keynote speeches. He Jun pointed out that the market demand for 3D packaging technology is experiencing explosive growth, and it is expected that by 2025, the global 3D packaging market value is expected to exceed the US$100 billion mark. Currently, TSMC is vigorously promoting the "3DFabric" platform, which integrates 3D packaging SoIC and 2.5D packaging CoWoS, InFO and other advanced packaging technologies. Thanks to 3D packaging technology, NVIDIA's latest generation GPU (H100) is 6 times more powerful than the previous generation (A100).

The strong demand for high-performance computing has driven the development of a large number of commercial applications of 3D packaging technology. It is expected that TSMC’s 3D packaging clean room space will more than double in 2025. In addition, TSMC is stepping up cooperation with ecological partners to jointly promote innovation in key 3D packaging technologies such as hybrid bonding to increase interconnect density and high bandwidth memory (HBM) memory signal integrity optimization.

Dr. Swaminathan, corporate vice president of AMD, said that the current demand for supercomputers and AI performance is increasing exponentially, doubling every 1.2 years, and demand has surged even more recently, tripling in one year. The industry is committed to achieving performance expansion at the system level through innovations such as high-speed interface design, advanced packaging and heterogeneous integration. AMD pays special attention to communication energy efficiency. Through the 3D stacking technology it is developing and the use of hybrid bonding packaging, the company can significantly reduce the energy consumption of communication between chips. It is expected to increase the performance per watt of HPC and AI training by 30 times in 5 years. .

To sum up, the two leading manufacturers representing wafer foundry and IC design respectively emphasize that the complementation of advanced packaging technology and next-generation AI architecture can lead to a significant improvement in chip computing capabilities.

Collaborative design will trigger major changes in AI, and high-density heterogeneous integration platforms will become the key to the future of semiconductors

This year’s conference held the IEEE EPS Forum for the third time. The host of the forum, Dr. Hong Zhibin, deputy general manager of ASE Group, said that IEEE EPS, as the organizer of the IMPACT conference, hopes to use this platform to gather the latest technologies and important speakers to promote the latest development trends of the industry. and technology exchange. The first IEEE EPS Forum focused on 5G, and the second forum discussed edge computing. This year, we specially teamed up with CEDA to jointly explore optimal ECAD tools for collaborative design between chips, packages, and systems. The idea of initiating the joint forum this time came from Dr. Bill Chen, senior technical consultant of ASE. In his remote speech, he said that although AI and machine learning have just started, they will continue to undergo significant changes in the next few decades. change. Co-design will drive the development of AI-related products and applications, which requires an open chip ecosystem and standard interfaces to achieve higher efficiency.

In addition, the joint forum also specially invited well-known scholars and experts from industry and academia at home and abroad to gather together, including Madhavan Swaminathan, Dean of the Department of Electrical Engineering at Pennsylvania State University, Hong Zhiming, Associate Director of MediaTek, Arvind Sundarrajan, Director of the Advanced Packaging Development Center of Applied Materials, and Georgia Institute of Technology Professor Sung Kyu Lim, Intel Senior Academician Debendra Das Sharma and Cisco Vice President Nan Wang jointly delivered speeches.

Professor Madhavan Swaminathan emphasized that high-density heterogeneous integrated platforms will become the future trend. We need to build a heterogeneous integrated platform from antennas to AI to support edge computing and communications. We also need to carry out technology development and collaborative design in many aspects, and decentralized Computing and communications are bound to play an important role. Dr. Hong Zhiming said on the topic of small chip AI-assisted design that collaboration in various aspects and fields including materials, machinery, EDA tools, etc. in different iterative design processes is very important, but it must be understood that not all links are suitable for AI. If you want to perform 3D AI machine learning must also consider whether there are mature enough tools for training.

Regarding the topic of hybrid bonding, Professor Madhavan Swaminathan pointed out that hybrid bonding is a key technology to promote AI and HPC, which can help process huge amounts of data, improve power consumption efficiency and reduce latency. But the hybrid bonding process is very complex, involving at least hundreds of steps. You cannot just optimize a single step, but require collaborative optimization to achieve better bonding yield. Professor Sung Kyu Lim believes that the second wave of AI revolution requires the coordinated operation of multiple chips. EDA tools help 2.5D and 3D chip packaging. They are not only the best assistant for designers, but also helpful for chip manufacturers because Current EDA tools can support material and bonding method decisions.

As for how the UCIe standard can expand the small chip ecosystem, Dr. Debendra Das Sharma pointed out that UCIe allows the mixing and matching of multiple chips at the packaging level to overcome process limitations and improve yield. Currently, the standard supports 2D and 2.5D packaging, and will also be used in the future. Support 3D. When building SoC systems on a single chip, UCIe can innovate at the packaging level. It can not only integrate CPU, GPU and memory, but also support interconnection standards such as USB, PCIe and CXL to create dynamically configurable systems. Vice President Nan Wang, who also talks about heterogeneous integration, said that OPC co-packaged optics can effectively solve the power consumption and cost challenges caused by machine learning training networks that require high-speed networking and large amounts of calculations. Through OPC technology, optical components can be placed close to the Ethernet Switch IC and packaged on the same substrate, reducing system power consumption by 30%, but it will also bring new challenges to signal and power integrity. . In this regard, co-design and optimization at the system level are needed to achieve large-scale application.

Seeking the best collaborative design tools to quickly respond to market heterogeneous integration needs

The second half of the IEEE & CEDA symposium was hosted by Dr. Chang Yaowen, Dean of the School of Electrical Engineering and Information Technology at National Taiwan University. He mainly raised three major topics, and on-site experts shared their insights. The first question raised first: "How can AI and advanced packaging solve the most difficult problems in AI and edge computing?" Professor Madhavan Swaminathan first responded by pointing out that AI requires large-scale computing and relies on the coordinated operation of chips of different technology nodes. . As for advanced packaging technology, it can realize the integration of chips in different fields such as RF, GPU, CPU and even optical components. Dr. Hong Zhiming shared the successful cases of AI in power supply analysis and chip layout optimization. However, insufficient data has become a bottleneck in expanding 3D, so human designers still cannot be replaced by AI. Professor Sung Kyu Lim said that the lack of circuit design data limits the application of supervised learning, and the academic community is increasing research efforts on unsupervised learning and reinforcement learning. Vice President Nan Wang believes that heterogeneous integration can solve network system problems, but it will inevitably increase the complexity of design and manufacturing.

The second topic is "Facing the next generation of AI and HI human intelligence, what are the key technical challenges that we must overcome? When will we see solutions to these challenges?" In this regard, Dr. Debendra Das Sharma believes that heterogeneous integration can Packaging computing and memory together, 3D stacking helps further shorten the distance, thereby reducing data transmission distance, improving performance and reducing power consumption. Dr. Arvind Sundarrajan pointed out that the key challenges brought by heterogeneous integration include reducing the spacing between wafers and substrates, defect control, bonding strength between different materials, and wafer warpage, etc., which requires technological innovation in materials and other aspects to obtain good results. performance.

Professor Zhang Yaowen finally asked: "How ready are EDA tools for advanced packaging? What are the key deficiencies that require immediate attention?" Professor Sung Kyu Lim said that EDA tools are lagging behind in heterogeneous integration, 2.5D and 3D. Designers More features and automation are needed. Although 2D EDA design tools are quite mature, there is still a lot of room for efforts in 3D integrated design. Professor Madhavan Swaminathan pointed out that the current EDA companies are too passive and are unwilling to invest in new technologies if there are no customer orders. EDA companies need to work with technology developers to jointly drive heterogeneous integration. Dr. Hong Zhiming believes that even for 2D design, internal tools need to be developed to supplement the shortcomings of commercial EDA tools, and EDA companies need to respond to designers’ needs faster. Dr. Debendra Das Sharma said that when EDA companies see market prospects, they will invest in new technologies. The key is that they can see that these technologies will become the next important direction. Vice President Nan Wang said that heterogeneous integration requires integrated analysis capabilities across different tools and systems such as EDA to prepare for various possible problems as early as possible.

This year's IMPACT 2023 was organized by the organizer in cooperation with many cooperating units. A total of 33 forums were held in three days. Not only did senior executives from TSMC and AMD deliver conference keynote speeches, but it also gathered hundreds of international leading manufacturers and academic researchers. Experts participated. This year, for the first time, IEEE EPS and IEEE CEDA Electronic Design Automation Society jointly held a joint forum, leading participants to explore the country of AI collaborative design. It also allowed IMPACT 2023 to not only delve into the technical level, but also expand to market trends, stimulating the spark of innovation!

The Taiwan Circuit Board Industry International Exhibition (TPCA Show 2023), which will be held at the same time, brings together 1,386 booths from around the world, exhibiting more than 480 international brands, focusing on forward-looking trends and technologies in semiconductor assembly, net-zero, and smart manufacturing, and actively providing opportunities for customers from all over the world. Global participants provide a variety of services, and the TPCA Show provides the industry with an excellent opportunity to showcase innovation and exchange cutting-edge technologies. We look forward to promoting industry development and demonstrating the excellence of Taiwan's PCBs.

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